Abstract

Two globally accepted techniques for dealing with the problem of long main memory latency are multithreading and memory hierarchy. Multithreading aims to hide long memory latencies by executing instructions from different threads when the one currently executing is issuing a long request. On the other hand, the insertion of one or more cache levels between the CPU and main memory attempts to minimize the response time allowing the CPU to work closer to its fast rates. Unfortunately the combination of the above techniques, especially in a single processor system, is not a trivial task. The effect of multithreading on the address referencing pattern affects both the temporal and spatial locality of programs on which principles of memory hierarchy design are based. We study the effect of different block sizes on the performance of both the cache and the processor. We find that although the miss rate is reduced as the block size increases the performance of the processor is either reduced or unaffected for a given memory bandwidth.